Embodiments of the present invention relate to memory devices, and more particularly to memory devices implementing a probe-based storage and reading mechanism.
As semiconductor devices continue to evolve and shrink in size in advanced technology nodes, increasing storage densities can be realized using semiconductor memories. Such memories include flash-based storage memories in which information can be stored in a non-volatile manner in transistors of the semiconductor device. More specifically, charge may be stored in a floating gate of such a device. However, charge can leak out of the floating gate over time, as the floating gate is in proximity to various conductors to enable its writing and reading. Further, as transistors of such devices are enabled with lower threshold voltages, reading the correct information from the transistor can become difficult, and charge leakage issues can become exacerbated.
Furthermore, semiconductor memories such as flash-based devices have a significant portion of their total area devoted to addressing the memory array. That is, various row and column decoders, as well as row and column lines are connected to the memory array. Furthermore, these conductors that connect to the individual transistors of the memory array can also provide a path through which charge leakage can occur.